The present invention relates to a probe unit substrate having a feature of planarization or leveling of probe mounting pads.
In this specification, the phrase “probe unit” signifies a unit having plural probes for testing electronic parts or electrical parts, and thus it corresponds to, for example, a probe card used for testing an electrical circuit on a semiconductor wafer or a probe unit used for testing a liquid crystal display. Further, the phrase “probe unit substrate” signifies a substrate for the probe unit, which has an internal wiring and is possible to support plural probes.
FIG. 11 is an enlarged sectional view illustrating a part of a conventional probe unit substrate. A ceramic substrate 10 has a surface, on which the first conductor layer 12 is formed in a predetermined pattern. Above the first conductor layer 12 are formed the first insulating layer 14, the second conductor layer 16, and the second insulating layer 18 in order. On the surface of the second insulating layer 18 are formed a number of probe mounting pads 20. Micro cantilever type probes 22 are fixed to the respective probe mounting pads 20. The first conductor layer 12 is formed to be a predetermined pattern, and includes through-hole Junction pads 24 and a grounding region 26. The ceramic substrate 10 is formed with through-holes 28, and inner conductors of the through-holes 28 are connected with the through-hole junction pads 24. The through-hole junction pad 24 is prepared for the purpose of absorbing a positional displacement, which might be caused by thermal contraction of the through-hole conductor of the ceramic substrate 10. The through-hole junction pads 24 are connected to the second conductor layer 16.
A clearance between the through-hole junction pad 24 and a grounding region 26 is filled with the first insulating layer 14 deposited therein. Accordingly, the surface of the first insulating layer 14 becomes not flat but shows undulation. Such undulation spreads to the second conductor layer 16 and the second insulating layer 18. Besides, if the second conductor layer 16 is formed in a predetermined pattern, other undulation resulting from the pattern is also added. As a result, undulation appears on the surface of the second insulating layer 18. If the probe mounting pad 20 rests on such an uneven surface of the second insulating layer 18, the surface of the probe mounting pad 20 would be in danger of being non-flat or being inclined from the horizontal condition even with flatness. Further, if the micro cantilever type probes 22 are fixed to the respective such probe mounting pads 20, it could lead to variation in heights of tips 30 of a number of probes 22.
The surface undulation of the first insulating layer 14 will be alleviated if the clearance between the through-hole junction pad 24 and the grounding region 26 is reduced. However, there is a restriction in reduction of the clearance, as will be described below. FIG. 12A is a plan view illustrating a pattern of the first conductor layer 12 around the through-hole junction pad 24. The clearance 32 (a space having no conductor layer) is formed around the through-hole junction pad 24, and thus the through-hole junction pad 24 is separated from the grounding region 26 with a distance d. The distance d is a hundred micrometers, for example.
Since the surface undulation of the first insulating layer 14 is caused by existence of the clearance 32, it would be possible to alleviate such undulation if the distance d is reduced. That is, as shown in FIG. 12B, it might be possible to reduce the distance d down to twenty-five micrometers for example. However, if the distance d is reduced, another problem occurs as described below. As shown in FIG. 12C, when a foreign particle 34 gets stuck in the clearance 32, there is a risk of short circuit between the through-hole junction pad 24 and the grounding region 26. Therefore, it is not very preferable to reduce the distance d. Much the same is true in the case of short circuit caused by any wrong pattern instead of the foreign particle 34.
FIG. 13 is a sectional view illustrating in a magnified form a part of another structure of the conventional probe unit substrate. In this probe unit substrate, a multilayer wiring division 42 is composed of the first conductor layer 12, the first insulating layer 14, the second conductor layer 16, the second insulating layer 18, the third conductor layer 54, the third insulating layer 56, the fourth conductor layer 58, the fourth insulating layer 60, the fifth conductor layer 62 and the fifth insulating layer 64. On the surface of the fifth insulating layer 64 are formed a number of probe mounting pads 20. This conventional structure brings, as well as the conventional structure as shown in FIG. 11, irregularity to the surface of the first insulating layer 14 caused by the fact that the first insulating layer 14 is deposited in the clearance between the through-hole junction pad 24 and the grounding region 26. In addition, for example, the wiring patterns formed in the second conductor layer 16 and the fourth conductor layer 58 bring the irregularity to the surfaces of the insulating layers 18 and 60 disposed above the conductor layers 16 and 58. These irregularities spill over into the uppermost surface of the fifth insulating layer 64 so that the surfaces of the probe mounting pads 20 would not be flat or would be inclined from the horizontal condition no matter how flat the surface is.
By the way, the technique regarding planarization of a multilayer wiring substrate is known as described below. Concerning the technique for fixing a probe to a conductor layer (which corresponds to the probe mounting pad) formed on the uppermost layer of the multilayer wiring substrate, an improvement in the surface flatness of the multilayer wiring substrate is disclosed in Japanese Patent Publication No. 2006-210473 A (the first publication).
In the first publication, a covering resin layer having through-holes is formed on an insulating base, and the through-holes are filled with conductor layers. Accordingly, the height of the surface of the covering resin layer is almost the same as the heights of the surfaces of the conductor layers, resulting in no irregularity. Then, an insulating resin layer and a wiring conductor layer can be formed above a combination of the above-described covering resin layer and the conductor layers. Accordingly, the surface irregularity of the multilayer wiring substrate is alleviated, and a conductor layer is formed on the surface of the multilayer wiring substrate and a number of probes are fixed to the conductor layer without variation in heights of the tips of the probes.
According to the above-described technique disclosed in the first publication, the surface irregularity of the multilayer wiring substrate is reduced, but the manufacturing process will be complicated to form “a covering resin layer having through-holes”. According to the first publication, formation of the through-hole in the covering resin layer requires 1) oxygen plasma treatment on the top side of the covering resin layer with the use of a metal layer as a mask, or 2) laser processing for removing a part of the covering resin layer to form through-holes.